Method and apparatus for reducing noise in a video signal

ABSTRACT

A noise reduction circuit in which a first signal (S  h2 ) is obtained by passing the input video signal (S  I  ) through a low frequency shut-off filter (10) and another a limiter (11), a second before signal (S  H21 ) is obtained by passing the above obtained signal (S  H2 ) through a field or frame delay circuit (5) and the difference between the two signals (S  H2  - S H21 ) is subtracted from the above input video signal (S  I  ) so as not to lower the definition of image, the noise reduction circuit being capable of application in a television receiver etc.

DESCRIPTION

1. Technical Field:

This invention relates to a noise reduction circuit for video signalsused in, for instance, a television receiver.

2. Background Art

As a noise reduction circuit used in a television receiver or the like,those shown in FIGS. 9 and 10 are hitherto known in which a delaycircuit such as a field memory (or a frame memory) is used.

FIG. 9 shows one forming an open-loop, in which input video signal S_(I)containing noise and fed at input terminal 1 is supplied to adders 2 and3, and is also supplied to A/D converter 4 for converting it into adigital signal. It is then written in to field memory 5, which functionsas a delay circuit. The digital signal read from memory 5 is convertedback into an analog signal S_(I1) by D/A converter 6. Accordingly, thisanalog signal S_(I1) is delayed by a field in relation to the abovesignal S_(I).

This signal S_(I1) is supplied to adder 2 and subtracted from the abovesignal S_(I) The difference signal S_(I) -S_(I1) between signal S_(I)and signal S_(I1) is obtained from adder 2 and is supplied to movementdetection circuit 7 and to multiplier 8. The above difference signalS_(I) -S_(I1) is considered a noise component if there is no movement ininput signal S_(I) within a field. In this case. difference signal S_(I)-S_(I1) is multiplied by coefficient k at multiplier 8 in accordancewith detection signal S_(M) from detection circuit 7 and then subtractedfrom signal S_(I) at adder 3. Therefore, output signal S_(o) in whichnoises are reduced is obtained from adder 3 at output terminal 9.

When a movement is detected by movement detection circuit 7, the abovedifference signal S_(I) -S_(I1) is considered to contain a movementcomponent so multiplier 8 reduces the value of K in accordance withsignal S_(M) from detection circuit 7 to reduce the quantity of themovement component subtracted at adder 3.

Movement detection circuit 7 detects the level of the above differencesignal S_(I) -S_(I1), and produces, detection signal S_(M) with whichcoefficient K of multiplier 8 is controlled. This movement detectioncircuit 7 may also be placed to compare the input signal and outputsignal of field memory 5 with each other as shown by dotted lines in thedrawing.

FIG. 10 shows an instance forming a closed loop, in which signal S_(I1)that a part which is output signal S_(o) delayed by a field in memory 5,is subtracted from signal S_(I) at adder 2 and that difference signalS_(I) -S_(I1) is passed through multiplier 8 and subtracted from signalS_(I) at adder 3. Thus, noise contained by signal S_(o) is graduallyremoved by feeding back signal S_(o), after delaying it by a field, sothat S_(o) is obtained from adder 3 with noise reduced.

A noise reduction circuit using a frame memory as disclosed by PatentKokai Sho 54-157429 is known.

DISCLOSURE OF THE INVENTION

The noise reduction circuit using a delay circuit such as a field memory(or a frame memory) as described above has need of both a memory oflarge capacity, to avoid lowering the definition of image, and amovement detection circuit so it has a defect in that the circuitconfiguration becomes large.

To overcome such a defect, in a noise reduction circuit according to thepresent invention, a difference signal is obtained which is thedifference between a signal obtained by passing the original videosignal through a low frequency shut-off filter and a limiter and thesignal obtained by passing that signal through a field or frame delaycircuit. The difference signal is then subtracted from the originalvideo signal.

According to the noise reduction circuit of the present invention thepart of the signal having an amplitude lower than a predetermined valueis taken out by the limiter from the high frequency component of thesignal obtained from the filter, and the difference in the field orframe of this signal is detected. Therefore, noise reduction is effectedwithout lowering the definition. A movement component is not containedby the high frequency component of the signal because any movementcomponent, is low frequency. Therefore, any signal difference in thefield or frame is considered a noise component.

Accordingly, in the noise reduction circuit of the present invention,the movement detection circuit used in a conventional noise reductioncircuit can be omitted and the definition of image is not lowered.Further, a field memory or a frame memory of especially large capacityis not required.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing a first embodiment of the invention;

FIGS. 2 are wave form charts of signals at points of FIG. 1;

FIG. 3 is a graph showing the characteristic of the limiter of FIG. 1;

FIG. 4 is a block diagram showing a second embodiment of the invention;

FIG. 5 is a circuit diagram showing an embodiment of a concrete circuitconfiguration of FIG. 4;

FIGS. 6 to 8 are circuit diagrams showing embodiments of a high-passfilter;

FIGS. 9 and 10 are block diagrams of conventional noise reductioncircuits.

THE BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows a first embodiment of the invention, in which partscorresponding to those of FIG. 9 are denoted by the same references asthose of FIG. 9 to omit the descriptions.

In FIGS. 1 and 2, input signal S_(I) containing noise N is applied toinput terminal 1 and thus supplied to adder 3 and to high-pass filter10, a low frequency shut-off filter. High frequency signal S_(H1)obtained from this high-pass filter 10 is supplied to limiter 11. Thislimiter 11 has the input to output characteristic shown in FIG. 3, inwhich a variable output signal is obtained between V₁ and V₂ of inputsignal and the output signal becomes constant when the level of inputsignal is out of the range between V₁ and V₂. Accordingly, any signalbetween V₁ and V₂ in the high frequency signal S_(H1), that is, signalS_(H2) containing a noise component, is obtained from limiter 11. Thissignal S_(H2) is supplied to adder 2 and delayed by a field through A/Dconverter 4, field memory 5 and D/A converter 6 to become signal S_(H21)and then subtracted from signal S_(H2) at adder 2.

The above high frequency signals S_(H2) and S_(H21) contain littlemovement component because the movement of image is low frequency ingeneral. Therefore, unless difference signal S_(H2) -S_(H21) obtainedfrom adder 2 is zero, it can be substantially considered a noisecomponent. Thus, this embodiment has no need of the movement detectioncircuit 7 of FIGS. 6 and 7 so it is omitted.

The above difference signal S_(H2) -S_(H21) is subtracted from inputsignal S_(I) at adder 3 after being multiplied by a coefficient K atmultiplier 8 to obtain signal S_(o) with reduced noise at outputterminal 9.

In this embodiment, since noise detection is effected with memory 5 inrelation only to signal S_(H2) which is of small amplitude since it hasbeen passed through limiter 11, the capacity of memory 5 can be smallerthan it would be if used to delay. The entire band of input signalS_(I), as shown in FIG. 9. Experiments have confirmed that the number ofbits of signal processed by D/A converter 4, memory 5 and D/A converter6 can be deceased from the conventional 8 bits to 6 bits.

FIG. 4 shows a second embodiment, in which parts corresponding to thoseof FIG. 1 are denoted by the same references as those of FIG. 1 to omitthe descriptions.

While the above first embodiment of FIG. 1 uses an open-loop, a closedloop is formed in this embodiment.

In FIG. 4, to become signal S_(H3), which that 12 signal S_(H2) ispassed through adder 12 is delayed by a field through A/D converter 4,field memory 5 and D/A converter 6 to be signal S_(H21), which is thensubtracted from signal S_(H2) at adder 2. Difference signal S_(H2)-S_(H21) obtained from adder 2 is supplied to adder 12 throughmultiplier 8 to be subtracted from signal S_(H2) to obtain the abovesignal S_(H3), which is fed back through memory 5. This embodiment is afeedback circuit in which field memory 5 is in a feedback loop anddifference signal S_(H2) -S_(H21) is obtained with signal S_(H21) fromthe feedback loop and S_(H2). As in the first embodiment, the differencesignal S_(H2) -S_(H21) is multiplied by coefficient K and thensubtracted from S₁ to obtain output signal S₀ having reduced noise.

FIG. 5 shows a concrete circuit configuration of each of circuit blocksof FIG. 4, in which parts corresponding to those of FIG. 4 are denotedby the same references as those of FIG. 4.

In FIG. 5, the above high-pass filter 10 comprises capacitor C₁ andresistances R₁ and R₂ and its cut-off frequency is selected to, forinstance, 500 KHz.

The above limiter 11 is constructed by connecting a differential circuitof transistors Q₁ and Q₂ and a differential circuit of transistors Q₃and Q₄ to each other in series through transistor Q₅. Voltage V₂ isapplied to the base of transistor Q₂ and voltage V₁ is applied to thebase of transistor Q₄. Accordingly, when signal S_(H1) is beyond V₂,transistor Q₁ is turned on so that its output signal is applied to thebase of transistor Q₃ through transistor Q₅. When this base voltage isbeyond V₁, transistor Q₃ is turned on so that its output signal isamplified by amplifier 15 comprising transistors Q₆, Q₇ and Q₈ to obtainsignal S_(H2) . The above transistor Q₅ compensates for the voltage dropbetween the base and emitter of transistor Q₁.

The above signal S_(H2) is supplied to A/D converter 4 after the outputof amplifier 8 (multiplier 8 in FIG. 4), comprising transistors Q₉ andQ₁₀ is added to create signal S₃. Signal S_(H3) is converted into, forinstance, a 6-bit digital signal by A/D converter 4 and reconverted intoanalog signal by D/A converter 6 after being delayed by 1-field memory5, and then inverted by inversion amplifier 13 comprising transistorsQ₁₁ and Q₁₂. This inverted signal is taken out as the above signalS_(H21), which is added to signal S_(H2) through resistances R₃ and R₄,and this sum signal is supplied to the above amplifier 8.

Signal, and S_(H2) -S_(H21) obtained as above is multiplied by amplifier8 and added to signal S₁ through resistances R₅ and R₆ to obtain outputsignal S_(o).

Although a field memory 5 is used in the first and second embodiments, aframe memory may also be used.

Next, high-pass filter 10 will be described.

If high-pass filter 10 is such a simple design as resistances R₁ and R₂capacitance C₁ as shown in FIG. 5, it is observed that noise is shiftedlaterally when to it is great, for instance, where the input fieldstrength is small and, the S/N ratio is bad. To improve this, if thefilter is made to have a group delay characteristic to equalize thedelay time independently of the frequency, the above phenomenon can besuppressed. An example of a high-pass filter of this case is shown inFIG. 6.

In FIG. 6, capacitance C₃ and resistance R₇ are connected in parallel toeach other, and a series circuit of resistance R₈ and capacitance C₄ isconnected parallelly to capacitance C₃.

As shown in FIG. 7, two high-pass filters 10₁ and 10₂ may be providedwhich are switched by switch 14. Here, high-pass filter 10₁ with thecut-off frequency of e.g., 500 KHz is constituted by capacitance C₁₁ andresistance R₁₁, and high-pass filter 10₂ with a cut-off frequency ofseveral KHz is constituted by capacitance C₁₂ and resistance R₁₂. Thesehigh-pass filters 10₁ and 10₂ are alternately selected with switch 14.

When noise is low, the cut-off frequency is set to a high frequency of500 KHz so as, not to eliminate any movement component. When noise isgreat, it may be helpful to reduce noise by lowering the cut-offfrequency to several KHz even with the resulting sacrifice of reductionof the movement component. The change-over may be effected manually withswitch 14 as shown in FIG. 7. Alternatively, switch 14 may beautomatically driven with a signal reflecting the input field strengthsuch as the AGC control voltage level of the tuner. Although thepreferred cut-off frequency of capacitance C₁₂ and resistance R₁₂ isseveral KHz, the cut-off frequency may be scores Hz or several Hz.

The high-pass filter may be comprised of a capacitance C and variableresistance R to vary the cut-off frequency continuously as shown in FIG.8. Variable resistance R may be controled manually or automatically inaccordance with the above AGC voltage so that the cut-off frequencyranges between 500 KHz and several Hz.

The detection of input field strength may also be effected by detectingthe noise level in a synchronizing signal rather than by utilizing theabove AGC voltage.

CAPABLE OF EXPLOITATION IN INDUSTRY

According to the present invention, the movement detection circuit whichis used in a conventional noise reduction circuit can be eliminated, andthe definition of image does not decrease. Further, it has no need of afield memory or a frame memory of especially large capacity. Therefore,the present invention is capable of application in a televisionreceiver, etc.

I claim:
 1. A method of reducing noise in a video signal,comprising:passing said video signal through a high pass filter tocreate a high frequency signal; passing said high frequency signalthrough a limiter to produce a first signal; delaying said first signalto produce a second signal; subtracting said second signal from saidfirst signal to produce a difference signal; subtracting said differencesignal from said video signal such that any noise in said video signalis reduced.
 2. A method according to claim 1 in which the step ofdelaying said first signal further comprises using a field delay circuitto delay said first signal.
 3. A method according to claim 1 in whichthe step of delaying said first signal further comprises using a framedelay circuit to delay said first signal.
 4. A method according to claim1 further comprising the steps of converting said first signal from ananalog signal to a digital signal prior to delaying said first signaland converting said delayed signal from a digital signal to an analogsignal prior to subtracting said second signal from said first signal.5. A circuit for reducing noise in a video signal, comprising:a highpass filter through which said video signal is passed to produce a highfrequency signal; a limiter through which said high frequency signal ispassed to produce a first signal, means for delaying said first signalto produce a second signal; means for subtracting said second signalfrom said first signal to produce a difference signal; means forsubtracting said difference signal from said video signal such that anynoise in said video signal is reduced.
 6. A circuit according to claim 5in which the means for delaying said first signal comprises a fielddelay circuit.
 7. A circuit according to claim 5 in which the means fordelaying said first signal comprises a frame delay circuit.
 8. A circuitaccording to claim 5 further comprising an analog to digital converterlocated between said limiter and said means for delaying said firstsignal and a digital to analog converter located between said means fordelaying said first signal and said means for subtracting said secondsignal from said first signal.
 9. A method of reducing noise in a videosignal, comprising:passing the video signal through a high pass filterto create a high frequency signal; passing the high frequency signalthrough a limiter to produce a first signal; passing the first signal toa junction; delaying the signal present at the junction to produce asecond signal; subtracting the second signal from the first signal toproduce a difference signal; subtracting the difference signal from thefirst signal at the junction; and subtracting the difference signal fromthe video signal such that any noise in the video signal is reduced. 10.A circuit for reducing noise in a video signal, comprising:a high passfilter through which the video signal is passed to produce a highfrequency signal; a limiter through which the high frequency signal ispassed to produce a first signal; an adder having as one input the firstsignal and as an output a second signal; means for delaying the secondsignal to produce a third signal; means for subtracting the third signalfrom the first signal to produce a difference signal; means forproviding the difference signal to said adder as a second and negativeinput such that the difference signal is subtracted from the firstsignal to produce the second signal; and means for subtracting thedifference signal from the video signal such that any noise in the videosignal is reduced.
 11. A circuit for reducing noise in a video signal,comprising:a high pass filter having an input and output, to which thevideo signal is input; a limiter having an input and output, the inputof which is connected to the output of the high pass filter; a firstadding means having two inputs and an output, one input of which isconnected to the output of the limiter; delay means having an input andoutput, the input of which is connected to the output of the firstadding means; a second adding means having two inputs and an output, oneinput of which is connected to the output of the limiter and the otherinput of which is a negative input and is connected to the output of thedelay means, and the output of which is connected to the second input ofthe first adding means as a negative input; a third adding means havingtwo inputs and an output, one input of which is the video signal and theother input of which is a negative input and is connected to the outputof the second adding means, and thus having as its output a video signalin which noise has been reduced.